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  • As shown in FIG. 2, the shown embodiment includes a memory controller MC, and a plurality of synchronous DRAMs M#i (i=0 to n, where n is a natural number not less than 1) parallel-connected to the memory controller MC, so that a read/write operation of the synchronous DRAMs M#i is controlled by the memory controller MC. This shown embodiment is so configured that, in a read operation of the sy
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