By way of example, FIGS. 4A-4C illustrate various operational modes in which the page length of the semiconductor memory device of FIG. 3 is varied based on the control signals PL0B and PL1B. In particular, FIG. 4A is a table that illustrates an operational mode in which both control signals PL0B and PL1B are deactivated/disabled (e.g., logic level high) to obtain a page length of 2n???2, wherein