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  • 2C is a plan view of a memory cell array included in the flash memory of the first embodiment, which shows a wiring pattern of a second-layer metal wiring layer; [0021] FIG. 2D is a plan view of a memory cell array included in the flash memory of the first embodiment, which shows a wiring pattern of a third-layer metal wiring layer; [0022] FIG. 3A is a sectional view taken along line 3A-3A of FIG.
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