EEPROM, according to one embodiment of the present invention, and circuit connections; [0120]FIG. 26 is a plan view of a semiconductor substrate showing a memory cell array of an EEPROM; [0121]FIG. 27 is an explanatory view showing a circuit connection for emission of electrons from a floating gate; [0122]FIG. 28 is an explanatory view showing a circuit connection for emission of electrons to a fl