ing operation for a system bus in the power control apparatus shown in FIG. 1 if a miss hit on a cache memory for data takes place;FIG. 4 is a timing chart for explaining an access cycle for a ROM;FIG. 5 is a flowchart showing a routine for accessing the ROM 16 in the idle state;FIG. 6 is a block diagram showing a power control apparatus for a computer system according to a second embodiment of th