he interface between MAIN-CPU and SUB-CPU;FIG. 27 is a timing chart which shows the transfer from MAIN-CPU to SUB-CPU;FIG. 28 is a timing chart which shows the transfer from SUB-CPU to MAIN-CPU;FIG. 29 to FIG. 78 are flow charts of the control circuit;FIG. 29 and FIG. 30 are drawings which show the main routine of MAIN-CPU;FIG. 32 to FIG. 63 are drawings which show the sub-routine of MAIN-CPU; and