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isa:156977997

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memory unit shown in FIG. 1; FIGS. 6A and 6B are a flow diagram of fetch cycle executed by the processor unit of FIG. 2; FIGS. 7A, 7B, and 7C are a flow diagram of an execute cycle executed by the processor unit of FIG. 2; FIGS. 8A and 8B are a flow diagram of a term cycle executed by the processor unit of FIG. 2; FIGS. 9A and 9B depict a timing unit for the processor unit of FIG. 2; FIG. 10 is

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n4:com

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isa:156977997