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FIGS. 11A to E show a method for manufacturing a lead frame used for manufacturing the semiconductor device according to Embodiment 6, where FIG. 11A is a plan view showing a surface-side resist pattern for etching, FIG. 11B is a plan view showing a schematic configuration of an electrode terminal, and FIGS. 11C to E are cross-sectional views showing states before etching, during etching and after
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