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3 is a diagram for explaining an access correspondence relationship of respective processing blocks to the memory shown on FIGS. 2A and 2B; [0029]FIG. 4 is a diagram for illustrating a configuration of a processing circuit shown in FIG. 1; [0030]FIG. 5 is a diagram showing a configuration of a frequency dividing circuit; [0031]FIG. 6 is a diagram showing a configuration of a frequency dividing cir
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