<http://webisa.webdatacommons.org/100047913>	<http://www.w3.org/ns/prov#value>	"FIG. 3A and FIG. 3B are a cross sectional configuration and an equivalent circuit diagram, respectively, of programming data to a first memory cell of the EEPROM device according to the present invention." .
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<http://webisa.webdatacommons.org/prov/450414110>	<http://www.w3.org/ns/prov#wasDerivedFrom>	<http://webisa.webdatacommons.org/100047913> .