<http://webisa.webdatacommons.org/prov/54774453>	<http://www.w3.org/ns/prov#wasDerivedFrom>	<http://webisa.webdatacommons.org/10337369> .
<http://webisa.webdatacommons.org/10337369>	<http://www.w3.org/ns/prov#value>	"value of the counted output of said counting means is zero, where N is a natural number greater than or equal to 2; a second counter reset responsive to the output detection signal of said first detecting circuit in a duration in which a detection signal is produced from said second detecting circuit, for counting pulses in said clock signal; and second decoder means for decoding a counted output" .
<http://webisa.webdatacommons.org/10337369>	<http://www.w3.org/ns/prov#wasQuotedFrom>	<freepatentsonline.com> .
<http://webisa.webdatacommons.org/10337369>	<http://www.w3.org/1999/02/22-rdf-syntax-ns#type>	<http://www.w3.org/ns/prov#Entity> .