<http://webisa.webdatacommons.org/prov/30028900>	<http://www.w3.org/ns/prov#wasDerivedFrom>	<http://webisa.webdatacommons.org/134503445> .
<http://webisa.webdatacommons.org/prov/450454247>	<http://www.w3.org/ns/prov#wasDerivedFrom>	<http://webisa.webdatacommons.org/134503445> .
<http://webisa.webdatacommons.org/prov/30809362>	<http://www.w3.org/ns/prov#wasDerivedFrom>	<http://webisa.webdatacommons.org/134503445> .
<http://webisa.webdatacommons.org/134503445>	<http://www.w3.org/ns/prov#value>	"FIGS. 2A and 2B are a schematic diagram and timing diagram, respectively, of a switched capacitor circuit according to the present invention;" .
<http://webisa.webdatacommons.org/134503445>	<http://www.w3.org/ns/prov#wasQuotedFrom>	<google.com> .
<http://webisa.webdatacommons.org/prov/450279122>	<http://www.w3.org/ns/prov#wasDerivedFrom>	<http://webisa.webdatacommons.org/134503445> .
<http://webisa.webdatacommons.org/134503445>	<http://www.w3.org/1999/02/22-rdf-syntax-ns#type>	<http://www.w3.org/ns/prov#Entity> .