<http://webisa.webdatacommons.org/prov/30144131>	<http://www.w3.org/ns/prov#wasDerivedFrom>	<http://webisa.webdatacommons.org/157815018> .
<http://webisa.webdatacommons.org/prov/31137437>	<http://www.w3.org/ns/prov#wasDerivedFrom>	<http://webisa.webdatacommons.org/157815018> .
<http://webisa.webdatacommons.org/157815018>	<http://www.w3.org/ns/prov#wasQuotedFrom>	<patents.com> .
<http://webisa.webdatacommons.org/157815018>	<http://www.w3.org/1999/02/22-rdf-syntax-ns#type>	<http://www.w3.org/ns/prov#Entity> .
<http://webisa.webdatacommons.org/157815018>	<http://www.w3.org/ns/prov#value>	"FIG. 3A and 3B is a block diagram showing a connection of transistors constituting a memory device provided in the tamper resistant module according to the embodiment of the present invention;" .