<http://webisa.webdatacommons.org/173303413>	<http://www.w3.org/ns/prov#value>	"The Flash memory system of claim 1, wherein the plurality of erase blocks are sequentially addressed and wherein the erase block pair of each super block are addressed Erase Block N and Erase Block N+Y, where N is a base address and Y is an offset. 14." .
<http://webisa.webdatacommons.org/173303413>	<http://www.w3.org/1999/02/22-rdf-syntax-ns#type>	<http://www.w3.org/ns/prov#Entity> .
<http://webisa.webdatacommons.org/173303413>	<http://www.w3.org/ns/prov#wasQuotedFrom>	<google.com> .
<http://webisa.webdatacommons.org/prov/516204729>	<http://www.w3.org/ns/prov#wasDerivedFrom>	<http://webisa.webdatacommons.org/173303413> .