<http://webisa.webdatacommons.org/175003096>	<http://www.w3.org/ns/prov#wasQuotedFrom>	<google.com> .
<http://webisa.webdatacommons.org/175003096>	<http://www.w3.org/1999/02/22-rdf-syntax-ns#type>	<http://www.w3.org/ns/prov#Entity> .
<http://webisa.webdatacommons.org/175003096>	<http://www.w3.org/ns/prov#value>	"FIGS. 3a and 3b taken together are a block diagram showing the sequence of operation of a read reorder matrix circuit compatible with the present invention." .
<http://webisa.webdatacommons.org/prov/30144135>	<http://www.w3.org/ns/prov#wasDerivedFrom>	<http://webisa.webdatacommons.org/175003096> .
<http://webisa.webdatacommons.org/prov/31137437>	<http://www.w3.org/ns/prov#wasDerivedFrom>	<http://webisa.webdatacommons.org/175003096> .