<http://webisa.webdatacommons.org/prov/250973366>	<http://www.w3.org/ns/prov#wasDerivedFrom>	<http://webisa.webdatacommons.org/183965626> .
<http://webisa.webdatacommons.org/183965626>	<http://www.w3.org/ns/prov#value>	"FIG. 11A is a plan view showing a part of a conventional EEPROM provided with memory cells, each composed of a floating gate memory cell transistor 121 and a select transistor 122." .
<http://webisa.webdatacommons.org/183965626>	<http://www.w3.org/ns/prov#wasQuotedFrom>	<google.com> .
<http://webisa.webdatacommons.org/183965626>	<http://www.w3.org/1999/02/22-rdf-syntax-ns#type>	<http://www.w3.org/ns/prov#Entity> .