<http://webisa.webdatacommons.org/222857013>	<http://www.w3.org/1999/02/22-rdf-syntax-ns#type>	<http://www.w3.org/ns/prov#Entity> .
<http://webisa.webdatacommons.org/222857013>	<http://www.w3.org/ns/prov#value>	"FIGS. 13A and 13B together are a circuit diagram of a second preferred embodiment of a sequential logic FPLA circuit according to the invention." .
<http://webisa.webdatacommons.org/prov/233231475>	<http://www.w3.org/ns/prov#wasDerivedFrom>	<http://webisa.webdatacommons.org/222857013> .
<http://webisa.webdatacommons.org/prov/235780149>	<http://www.w3.org/ns/prov#wasDerivedFrom>	<http://webisa.webdatacommons.org/222857013> .
<http://webisa.webdatacommons.org/222857013>	<http://www.w3.org/ns/prov#wasQuotedFrom>	<patents.com> .