<http://webisa.webdatacommons.org/250152305>	<http://www.w3.org/ns/prov#wasQuotedFrom>	<google.fr> .
<http://webisa.webdatacommons.org/250152305>	<http://www.w3.org/1999/02/22-rdf-syntax-ns#type>	<http://www.w3.org/ns/prov#Entity> .
<http://webisa.webdatacommons.org/250152305>	<http://www.w3.org/ns/prov#value>	"FIG. 12A is a diagram showing an exemplary allocation of reconfigurable hardware resources between the Instruction Fetch Unit, the Data Operate Unit, and the Address Operate Unit for an outer-loop Instruction Set Architecture;" .
<http://webisa.webdatacommons.org/prov/236814859>	<http://www.w3.org/ns/prov#wasDerivedFrom>	<http://webisa.webdatacommons.org/250152305> .