. . . "B is a schematic diagram illustrating the respective capacitances between the between respective components of the novel memory cell shown in FIG. 2A.FIG. 2C is a simplified schematic diagram representing the same capacitance relationship shown in FIG. 2B.FIG. 3A is a block diagram of another, asymmetrical embodiment for a novel memory cell, transistor, or floating gate transistor formed according" .