<http://webisa.webdatacommons.org/prov/231779237>	<http://www.w3.org/ns/prov#wasDerivedFrom>	<http://webisa.webdatacommons.org/278289850> .
<http://webisa.webdatacommons.org/278289850>	<http://www.w3.org/1999/02/22-rdf-syntax-ns#type>	<http://www.w3.org/ns/prov#Entity> .
<http://webisa.webdatacommons.org/278289850>	<http://www.w3.org/ns/prov#value>	"FIG. 12, consisting of FIGS. 12A and 12B, is a circuit diagram illustrating a zero generation circuit according to one embodiment of the present invention." .
<http://webisa.webdatacommons.org/278289850>	<http://www.w3.org/ns/prov#wasQuotedFrom>	<patents.com> .
<http://webisa.webdatacommons.org/prov/236814908>	<http://www.w3.org/ns/prov#wasDerivedFrom>	<http://webisa.webdatacommons.org/278289850> .