<http://webisa.webdatacommons.org/prov/464323334>	<http://www.w3.org/ns/prov#wasDerivedFrom>	<http://webisa.webdatacommons.org/282756434> .
<http://webisa.webdatacommons.org/282756434>	<http://www.w3.org/ns/prov#wasQuotedFrom>	<google.com> .
<http://webisa.webdatacommons.org/282756434>	<http://www.w3.org/ns/prov#value>	"FIGS. 8A and 8B are a flow chart for explaining degenerate code generation processing and maps of main registers according to a second embodiment of the present invention;" .
<http://webisa.webdatacommons.org/282756434>	<http://www.w3.org/1999/02/22-rdf-syntax-ns#type>	<http://www.w3.org/ns/prov#Entity> .
<http://webisa.webdatacommons.org/prov/464780395>	<http://www.w3.org/ns/prov#wasDerivedFrom>	<http://webisa.webdatacommons.org/282756434> .