"urth specific embodiments of respective FIGS. 5A, 5B and 7A, 7B; FIG. 9 is a block diagram of a flash EEPROM system that utilizes the memory cells of either of the first or third specific embodiments of respective FIGS. 4A, 4B and 6A, 6B; FIGS. 10A and 10B show in cross-section an intermediate structure which occurs during the formation of the third cell array embodiment of FIGS. 6A and 6B, taken" . . . .