. . . "e);FIG. 9 is a timing chart showing the DDR read operation of a synchronous DRAM according to the first embodiment of the present invention;FIGS. 10A and 10B are circuit diagrams each showing the operation of a read data line control circuit (in the DDR scheme);FIG. 11 is a timing chart showing the SDR read operation of the synchronous DRAM according to the first embodiment of the present inventio" .