<http://webisa.webdatacommons.org/prov/232653306>	<http://www.w3.org/ns/prov#wasDerivedFrom>	<http://webisa.webdatacommons.org/96208292> .
<http://webisa.webdatacommons.org/96208292>	<http://www.w3.org/ns/prov#wasQuotedFrom>	<google.com> .
<http://webisa.webdatacommons.org/96208292>	<http://www.w3.org/1999/02/22-rdf-syntax-ns#type>	<http://www.w3.org/ns/prov#Entity> .
<http://webisa.webdatacommons.org/96208292>	<http://www.w3.org/ns/prov#value>	"FIGS. 20a and 20b are a simplified block diagram of a pre-processing circuit PREC, in accordance with the present invention and are collectively FIG. 20;" .
<http://webisa.webdatacommons.org/prov/231790180>	<http://www.w3.org/ns/prov#wasDerivedFrom>	<http://webisa.webdatacommons.org/96208292> .