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n5google.
isaphttp://webisa.webdatacommons.org/prov/
isahttp://webisa.webdatacommons.org/
rdfhttp://www.w3.org/1999/02/22-rdf-syntax-ns#
provhttp://www.w3.org/ns/prov#
xsdhhttp://www.w3.org/2001/XMLSchema#
Subject Item
isa:405687184
rdf:type
prov:Entity
prov:value
The status of memory cells is detected by verify operations for determining whether PROGRAM or ERASE is completed, and LOAD SIGNAL SLD may be shifted from the logic high state to the logic low state in response to detecting that verification of a predetermined number of memory cells is completed.
prov:wasQuotedFrom
n5:com
Subject Item
isap:318699778
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