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  • FIGS. 7A and 7B illustrate a plan view and a cross-sectional view of a semiconductor device, respectively, and FIG. 7A is a plan view of a semiconductor device and FIG. 7B is a cross-sectional view taken along line C-D in FIG. 7A. An external terminal connection region 202 to which an FPC is bonded, a sealing region 203, a peripheral driver circuit region 204, and a pixel region 206 are provided.
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