For instance, as shown in FIG. 12, a pair of MIS's QL1, QL2 for load resistance may be arranged as having an offset structure (as indicated by thick lines), and if circuits other than SRAM exist in a pair of MIS's Qd1, Qd2 for drive, a pair of MIS's Qt1, Qt2, a peripheral circuit of SRAM and the same semiconductor chip, MIS's constituting the logic circuits may be arranged as having a non-offset s