odiment comprises, as shown in FIG. 4, an input use clock generation circuit 11, an output use clock generation circuit 12, a clock use buffer 13, a semiconductor circuit 14, data input/output circuits 15-1 to 15-n (note that n is a positive integer), and data input/output terminals TI/O1 to TI/On as main components. [0077] Note that only a circuit affixed the reference number 15-1 is shown the sp