FIG. 14 illustrates the NAND2 gate standard cell 108 b having optional metal 1 (M-1) power bus lines 414 b which may be used to interconnect down to the power buses 412 b of FIG. 13 when resistance is an issue in an integrated circuit design, or minimizing the number of power straps 106 is desired (i.e., making wider power strap separations).