This means that O1 can output any one of A, B, C, or D, while O2 can output any one of E, F, G, H. Thus, if for example the registers are arranged so that A to D are the even numbered registers and B to H are the odd register numbers then O1 will be able to read an even register and O2 an odd register, and vice versa if the multiplexers in the final layer are switched the other way round.