Two systems of the relevant wirings and circuits such as decoders are not required for theauxiliary cell array 12, which leads to making the circuit area smaller.In a case that the prefetch of the address driver 15 ranges from the first bit-line address Y0 on the word-line address Xk of the memory cell array 11 to the last bit-line address Yn of the previous word-line address Xj thereof, the data