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  • t diagram of the memory cell array and the bit line control circuit of the embodiment of FIG. 2.FIGS. 4A and 4B are a schematic cross sectional view of a memory cell and that of a selection transistor that can be used for the first embodiment.FIG. 5 is a schematic cross sectional view of a NAND cell that can be used for the first embodiment.FIG. 6 is a schematic circuit diagram that can be used fo
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