FIG. 9A is a diagram for explaining the phase of the output turret and the balancer turret at the time points t0 and t4, FIG. 9B is a diagram for explaining the phase of the output turret and the balancer turret at the time points t1 and t3, and FIG. 9C is a diagram for explaining the phase of the output turret and the balancer turret at the time point t2.