For example, in view of the 16 glyph???16 glyph dimensions of the frame blocks 72 for this particular implementation, each of the address codes suitably is a nine element, maximal length shift register code (i.e., a nine bit wide PNS) which is encoded in the lattice glyphs at a two third (2/3) duty cycle (i.e., two out of every three glyphs in the lattice frame encode address code).