Referring to FIG. 2, the data I/O circuit 100 includes a plurality of page buffers PB11 to PBM(K+J) (where each of M, K and J is an integer), a plurality of page buffer select circuits PS11 to PSM(K+J), precharge circuits PG1 to PG(K+J), column select circuits CA1 to CAL (where L is an integer), a sense amplifier 110 and an input circuit 120.