The signal 1135I is filtered by LPF 1140_I and digitized into a first output signal BB_I using ADC 1150_I, while the signal 1135Q is filtered by LPF 1140_Q and digitized into a second outputsignal BB_Q using ADC 1150_Q. PLL 1160 is used to generate a clock signal CLK, whose frequency is for example 12 times as high as the frequency of the desired RF signal to be converted.