prov:value
| - In this and following Figures, the notation `S1[a], S2[b], . . . , SM[Z]`, where S is an arbitrary signal label and a,b, . . . , z are integers within the range of the signal's bus width, indicates that the selected bits a, b, . . . , z from the signals S1, S2, . . . , SM are transferred in parallel over the same bus, with the most significant bits (MSBs) being the selected bits `a` of the signal
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