In selected embodiments, the metal-based layer 25 is deposited on the second high-k gate dielectric layer 24 using any desired deposition or sputtering process, such as CVD, PECVD, PVD, ALD, molecular beam deposition (MBD) or any combination(s) thereof A suitable material for use as the metal-based layer 25 is an element or alloy (e.g., TaC or W) which may be deposited over the NMOS and PMOS regio