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  • Referring to FIGS. 7A and 7B, FIG. 7A is a schematic top view of a patterned second resist layer in the practice of the invention of the present invention and FIG. 7B shows a schematic cross section of a chip along line BB??? in FIG. 7A. A second resist layer 48 having substantially parallel second trench patterns 46 is formed on the cured first resist layer 42.
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