DESCRIPTION OF DRAWINGS [0003]FIG. 1 is a block diagram of a communication system employing a hardware based multithreaded processor. [0004] FIGS. 2-1 to 2-4 are a detailed block diagram of a hardware based multithreaded processor of FIG. 1. [0005]FIG. 3 is a block diagram depicting a functional arrangement of the multithreaded processor of FIG. 2. [0006]FIG. 4 is a block diagram depicting data st