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  • B is a block diagram of a computer system coupled to a separate storage box implementing an array controller implemented according to the present invention; [0019]FIG. 2 is a block diagram of the array controller of FIG. 1A or 1B that includes a processor, processor memory, memory controller and transfer buffer memory; [0020]FIG. 3A is a figurative diagram illustrating a read modify write (RMW) op
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