The image-processing apparatus includes a CPU 1 that controls individual components of the image-processing apparatus, a ROM 2 that stores programs and the like, a bus bridge 3, m image-processing modules 4-1 to 4-m (collectively referred to as an image-processing module 4) where m is an integer greater than one, a DRAM 7, an arbiter 5 that arbitrates access to the DRAM 7, a DRAM interface 6, a he