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  • The output bias logic 301 is coupled to bias adjust logic 303 via signals PADD[3:0] and PSUBEN. Signals INT BCLK and SUM[5:0] are routed to the bias adjust logic 303, which produces corresponding signals PSUM_X[5:0] as shown in FIG. 1. [0037] In operation, during selected cycles of the clock signal INT BCLK, such as every other clock cycle or the like, the bias adjustment logic 303 adjusts (e.g.,
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