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  • The output bias logic 701 is coupled to bias adjust logic 703 via signals ADD[3:0] and SUBEN. Signals INT BCLK and SUM[5:0] are routed to the bias adjust logic 703, which produces corresponding signals OSUM_X[5:0] as shown in FIG. 5. [0049] In operation, during selected cycles of the clock signal INT BCLK, such as every other clock cycle or the like, the bias adjustment logic 703 adjusts (e.g., in
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