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  • When addresses 15F5H, 15F6H, and 15F7H are selected, 20-bit shift register 123 outputs the 20-bit data D2 12 to D2 15, D3 0 to D3 7, and D3 8 to D3 15 obtained by adding to the 20-bit data stored therein bit 0 to bit 7 (bit data Rev0 to Rev7) of the signal composed of the signals other than the address signal and the data signal and bit 12 to bit 19 (bit data A12 to A19) of the 20-bit address sign
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