FIGS. 103 and 104 are top plan views of the memory cell array; FIG. 105 is a cross-sectional view taken along the line CV-CV in FIGS. 103 and 104; and FIG. 106 is a cross-sectional view taken along the line CVI-CVI in FIGS. 103 and 104. [0488] It should be noted that for facilitating the understanding of the figures, FIG. 103 omits a wiring layer in which bit lines are formed, and FIG. 104 shows o