FIGS. 109 and 110 are top plan views of the memory cell array; FIG. 111 is a cross-sectional view taken along the line CXI-CXI in FIGS. 109 and 110; and FIG. 112 is a cross-sectional view taken along the line CXII-CXII in FIGS. 109 and 110. [0517] It should be noted that for facilitating the understanding of the figures, FIG. 109 omits a wiring layer in which bit lines are formed, and FIG. 110 sho