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  • A, 13B, and 13C; [0035]FIG. 15 is a circuit diagram illustrating the internal structure of the secondary decision circuits in FIGS. 13A, 13B, and 13C; [0036]FIG. 16, consisting of FIGS. 16A, 16B, and 16C, is a block diagram of a semiconductor memory device illustrating a third embodiment of the invention; [0037]FIG. 17, consisting of FIGS. 17A, 17B, and 17C, is a block diagram of a semiconductor m
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