Each of the NOR gates is typically identical in configuration and manner of operation to NOR gate A or B of FIG. 3A. For each sensor row 22 and 23, the memory output signal on line 82 for each sensor except the one farthest from the player is inverted at C and is then supplied as a normally plus input to NOR circuit D. The other input to D is taken via the line 92 directly from the memory output f