FIGS. 3A and 3B are a cross-sectional side view and a corresponding doping concentration view, respectively, illustrating a conventional symmetrically formed floating gate transistor used as a memory cell of a FLASH or EEPROM array of FIGS. 2A and 2B, formed using a FLASH or EE mask pattern that determines FLASH/EEPROM regions to be implanted by two symmetric halo implants from opposing directions